Conventional Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) utilize poly-silicon for forming gate electrodes, in view of its good thermal stability, i.e. its ability to withstand high temperature processing. More specifically, the good thermal stability of poly-silicon-based materials permits high temperature annealing thereof during formation/activation of implanted source and drain regions. In addition, poly-silicon-based materials advantageously block implantation of dopant ions into the underlying channel region of the transistor, thereby facilitating formation of self-aligned source and drain regions after gate electrode deposition and patterning are completed.
However, poly-silicon-based gate electrodes have a number of problems associated therewith, as a result of which, CMOS structures have been proposed in which two different materials are used as the gate materials for respective NMOS and PMOS devices, and suitable integration techniques are therefore required.
There are currently two such integration techniques proposed. A first technique, known as a dual metal gate process, consists of deposition of a first electrode material A with work function φA on both NMOS and PMOS devices, its complete removal on one transistor type, and then uniform deposition of a second gate electrode material B with work function φB, followed by the final gate patterning process. However, a major difficulty arises in this technique, in respect of the complete removal of the first gate electrode material without damaging the gate oxide.
A second technique is described in U.S. Pat. No. 6,518,154, in which a process is described for fabricating a semiconductor device including a plurality of active devices, such as NMOS and PMOS transistors, formed on a common semiconductor substrate. In the described process, a first blanket layer of a first metal is deposited over a gate insulator layer provided on the substrate, then a masking layer segment is laid over the layer of metal in the region of the first active device and a second blanket layer of a second metal or semi-metal is deposited over the upper surface of the resultant structure covering the masked and unmasked upper surface thereof. The structure is then subjected to a thermal treatment at an elevated temperature in an inert atmosphere for effecting an alloying or silicidation reaction between the first and second blanket layers where they are in contact (i.e. in the region of the second active device), whereas the masking segment prevents such alloying or silicidation in the region of the first device. The second blanket layer and masking segment are then removed from the region of the first active device, leaving a first gate electrode layer of the first material in the region of the first device and a second gate electrode layer of the alloyed first and second materials in the region of the second active device. Finally, the gate electrode layers are patterned.